Since the mid-1990's so-called damascene processes have been the dominant technology for forming conductive interconnect in integrated circuits. Those skilled in the art recognize that damascene processing involves forming opening (via and trenches) in a dielectric layer and then filling the openings with a conductive, typically copper. The copper is typically deposited by initially depositing a thin seed layer within the openings and then filling the opening by electroplating copper.
One disadvantage of the prior art is that forming openings in the dielectric layer requires etching the dielectric layer. This etch process may damage the dielectric layer, particularly as the industry trends progress toward lower dielectric constant (low k) dielectric layers, which are more vulnerable to damage from the etching process. Increased leakage current, reduced dielectric constant, and reduced performance and reliability may result from the etch-induced damage to the dielectric layer.
Another disadvantage of the traditional damascene approach is that the etching processes can also damage a barrier layer that is frequently used to line the opening prior to deposition of the copper. Furthermore, subsequent thermal processing may sometimes cause the copper features within the openings to deform, such as to form a hump in the center, which can negatively impact the device performance and reliability.
What is needed then is a interconnect structure and method of forming same that overcomes or reduces the disadvantages of the prior art.